Training for high-qualified engineers
The Ministry of Electronics and Information (MeitY) has sought applications from 100 academia, R&D organisations, start-ups and MSMEs under its Chips to Startup (C2S) Programme. The C2S programme aims to train 85,000 number of high-quality and qualified engineers in the area of Very large-scale integration (VLSI) and embedded system design as well as result in development of 175 ASICs (Application Specific Integrated Circuits), working prototypes of 20 System on Chips (SoC) and IP Core repository over a period of 5 years.
C-DAC (Centre for Development of Advanced Computing), a scientific society operating under MeitY, will serve as the nodal agency for the programme. Online applications are open at the Chips to Startup (C2S) website until January 31.
Programme in 100 institutions
The project proposals should be submitted at C2S portal (www.c2s.gov.in) in the format prescribed at the portal. The institutions applying under the programme should meet the eligibility criteria defined at the portal and should be in line with the proposals’ guidelines.
This, the government says, will be a step towards leapfrogging in the Electronics System Design and Manufacturing (ESDM) space by way of inculcating the culture of SoC/ System Level Design at Bachelors, Masters and Research level and act as a catalyst for growth of start-ups involved in fabless design. The programme would be implemented at about 100 academic institutions, R&D organisations across the country, including IITs, NITs, IIITs, Government/Private Colleges and R&D organisations.
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Startups can participate
Startups and MSMEs can also participate in the programme by submitting their proposals under the Academia-Industry Collaborative Project, Grand Challenge/Hackathons/RFP for development of System/SoC/IP Core(s).
The C2S Programme addresses each entity of the value chain in electronics viz. quality manpower training, research and development, hardware IPs design, system design, application-oriented R&D, prototype design and deployment with the help of academia, industry, start-ups and R&D establishments.
Under the Programme, based on the Institutions’ expertise, Technology Readiness Level (TRL) and design experience acquired during earlier SMDP Programmes, proposals are invited in three different categories, i.e., Design and Development of Systems/SoCs/ASICs/Reusable IP Core(s), Development of Application Oriented Working Prototype of IPs/ASICs/SoCs, and Proof of Concept oriented Research and Development of ASICs/FPGAs.
